Computer input/output (I/O) performance has become crucial to applications today because of the use of the Internet, intranets, and extranets. Key applications deployed in most Information Technology (IT) enterprises are typically predicated upon I/O subsystem performance in handling key I/O tasks to deliver data to and from computer's main CPU. These applications may include all Internet applications ranging from Web severs to Internet-based e-commerce and TCP/IP network handling, mail and messaging, on-line transaction processing, and key packaged decision-support applications. Other IT infrastructure changes have also increased the burden on computer server I/O.
Emerging solutions to many of the current server I/O shortcomings include the “Next Generation I/O” (NGIO) technology which provides a channel oriented, switched fabric, serial link architecture designed to meet the growing needs of I/O reliability, scalability and performance on commercial high-volume servers. Next Generation I/O introduces the use of an efficient engine that is coupled to host memory which replaces shared buses with a fabric of switchable point-to-point links. This approach decouples the CPU from the I/O subsystem and addresses the problems of reliability, scalability, modular packaging, performance and complexity. Communication between CPU and peripherals occurs asynchronously with the I/O channel engine. The I/O channel engine is utilized to transport data to and from main memory and allow the system bus to act as a switch with point-to-point links capable of near linear scaling with CPU, memory and peripheral performance improvements.
One challenge to implementing a computer network which utilizes an NGIO architecture is to ensure that high-speed data communications between a data transmitter (source node) and a data receiver (destination node) operating in two different clocks are synchronous with respect to the transmission and reception of data within each data packet. Such data transmitter and data receiver may correspond to different nodes of a computer network which operate in synchrony with different clock signals. Failure to maintain synchronism between the data transmitter and data receiver may result in mis-communication and therefore, effective loss of data.
One method commonly employed to establish data synchronization between a data transmitter and a data receiver in a computer network is the use of an elastic buffer which can elastically compensate for any time difference in the transmitter rate and the receiver rate. Conventional elastic buffers may typically be implemented to dynamically adjust the data rate of a data stream so as to synchronize the data transmitter with the data receiver. There are, however, a number of problems associated with the use of conventional elastic buffers. One major problem is known as a data overflow/underflow which pertains to the need to ensure that data is read from the buffer in the same order that it was written to the buffer. Reading data that has not been written or writing data over data that has not yet been read may destroy the integrity of the data packet being transferred between the data transmitter and the data receiver. Another problem relates to the proper control of the elastic buffer and the network specific application.
Since NGIO is an emerging technology not yet in the marketplace, there is no known elastic buffer specifically implemented for NGIO application. There is no advanced elastic buffer design for transitioning link data from a NGIO link which operates in a Link Clock Domain into a data receiver which operates in a Receiver Clock Domain. Moreover, there is no circuit design for an NGIO link architecture implemented to prohibit data overflow which can corrupt the received Link Data and data underflow which can corrupt the Receiver Data being processed.
Accordingly, there is a need for an advanced Elastic Buffer provided to process data in a computer network using an NGIO link architecture, and an especially designed mechanism for preventing such an Elastic Buffer from data overflow under any conditions while enhancing reliability of Elastic Buffer operation and ensuring data integrity at the receiver interface.